Priority Date: 05.06.13 (US 201361831400P)

SELECTIVE PARTITIONING OF VIA STRUCTURES IN PRINTED CIRCUIT BOARDS

  • Application ID: EP14729483
  • Status: PATENT GRANTED

Applicant

Technology company logo small
Technology Company

Attorney

Technology company logo thumb
no operation time available
4 offices
Technology Company

Specialization

This patent has the IPC class H05 (ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR) is specialized in H05. Here you find a list of all patent agent firms which are specialized in this IPC class. For a similar patent, they might be a good choice.

Timeline

  • 05.06.2013 - Priority Date (US 201361831400P)
  • 11.12.2014 - Publication A1 (WO2014196911)
  • 15.07.2015 - Publication A1 (EP2893784)
  • 05.10.2016 - Publication B1 (EP2893784)

IPC Classification